參數(shù)資料
型號: XPC823CVR66B2T
廠商: Freescale Semiconductor
文件頁數(shù): 62/70頁
文件大小: 0K
描述: IC MPU POWERQUICC 66MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC823 ELECTRICAL SPECIFICATIONS
65
Tcyc is the cycle time of the LCD clock (shift clock). Tdelay is a circuit delay that is specified in
the AC electrical specifications. 116 lines is a time period that can vary between one scan line
and 16, depending on how the LCD controller is programmed in the VPW field of the LCVCR.
01,023 lines is a time period that can vary between 0 and 1,023 scan lines in the WBF field of
the LCVCR.
Table 21. LCD Controller Timing
NUM
CHARACTERISTIC
25MHZ
40MHZ
50MHZ
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
220
Shift clock cycle time
40
40
40
nsec
221
Shift clock high time
20
20
20
nsec
223
CLOCK/HSYNC/VSYNC/OE rise and fall
times
10
10
10
nsec
224
Data valid delay from shift clock high
15
15
15
nsec
225
VSYNC to HSYNC setup time1
555
T
226
VSYNC hold time
111
T
227
HSYNC pulse width
444
T
228
Time from clock falling edge to HSYNC
rising edge
4.5
4.5
4.5
T
229
Time from HSYNC falling edge to clock
rising edge2
444
T
230
AC active delay
25
25
25
nsec
231
VSYNC pulse width (TFT)
1
16
1
16
1
16
Line
232
HSYNC to OE delay3
444
T
233
OE to HSYNC delay
444
T
234
VSYNC to OE delay (TFT)
0
1,023
0
1,023
0
1,023
T
235
VSYNC/HSYNC/OE active delay (TFT)
15
15
15
nsec
236
Wait between frames4
WBF
WBF
WBF
Line
NOTES:
1.
T = shift clock cycle (220).
2.
This number is given for wbl(wait between lines)
2. For wbl=n {n>2} the timing will be (n+2)T.
3.
This number is given for wbl(wait between lines)
2. For wbl=n {n>2} the timing will be (n+2)T.
4.
Wait Between Frames (WBF) is a programmable parameter.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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