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參數(shù)資料
| 型號： | XPC8240LZU200E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 0K |
| 描述： | MCU HOST PROCESSOR 352-TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
MPC8240 Part Number Specification for the XPC8240RXXnnnx Series
3
General Parameters
1.4.1.5 Power Characteristics
Table 5 provides power consumption data for the MPC8240. Power consumption on the PLL supply pins (AVDD
and AVDD2) and the DLL supply pin (LAVDD) less than 15 mW. This parameter is guaranteed by design and is not
tested.
Die-junction temperature
Tj
0 to 105
°C
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. These signals are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3- or 5.0-V DC power
supply.
3. LVDD input tolerant signals: PCI interface, EPIC control, and OSC_IN signals.
Cautions:
5. Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2/LAVDD) by more than 2.5 V at all
times, including during power-on reset.
6. OVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7. VDD/AVDD/AVDD2/LAVDD must not exceed OVDD by more than 0.6 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. GVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. LVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 5.4 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10.LVDD must not exceed OVDD by more than 3.6 V at any time, including during power-on reset. This limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
Table 5. Preliminary Power Consumption
Mode
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Unit
Notes
33/66/233
33/83/250
33/100/200
33/100/250
66/100/200
66/100/250
Typical
3.4
3.6
3.2
3.7
3.2
3.8
W
1, 5
Maximum—FP
3.8
4.1
3.6
4.2
3.6
4.3
W
1, 2
Maximum—INT
3.4
3.7
3.3
3.8
3.4
3.8
W
1, 3
Doze
2.2
2.4
2.2
2.6
2.2
2.6
W
1, 4, 6
Nap
700
800
900
mW
1, 4, 6
Sleep
500
800
mW
1, 4, 6
I/O Power Supplies
Mode
Minimum
Maximum
Unit
Notes
Typical—OVDD
200
600
mW
7, 8
Table 2. Recommended Operating Conditions (continued)
Characteristic
Symbol
Recommended
Value
Unit
Notes
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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