參數(shù)資料
型號(hào): XPC8240RZU250E
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 0K
描述: MCU HOST PROCESSOR 352-TBGA
標(biāo)準(zhǔn)包裝: 24
系列: MPC82xx
處理器類(lèi)型: 32-位 MPC82xx PowerQUICC II
速度: 200MHz
電壓: 2.5V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 352-LBGA
供應(yīng)商設(shè)備封裝: 352-TBGA(35x35)
包裝: 托盤(pán)
4
MPC8240 Part Number Specification for the XPC8240RXXnnnx Series
PLL Configurations
1.5
PLL Configurations
The MPC8240 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN
(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)
frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)
frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the
MPC8240 is shown in Table 18.
Typical—GVDD
300
900
mW
7, 9
Notes:
1. The values include VDD, AVDD, AVDD2, and LAVDD but do not include I/O supply power; see Section 1.7.2, “Power
Supply Sizing,” in the MPC8240 Integrated Processor Hardware Specifications for information on OVDD and GVDD
supply power. One DIMM is used for memory loading.
2. Maximum—FP power is measured at VDD = 2.625 V with dynamic power management enabled while running an
entirely cache-resident, looping, floating point multiplication instruction.
3. Maximum—INT power is measured at VDD = 2.625 V with dynamic power management enabled while running
entirely cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at VDD = 2.625 V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at VDD = AVDD = 2.625 V, OVDD = 3.3 V where a nominal FP value, a nominal INT value,
and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries
to local memory are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values were results of the MPC8240 performing cache resident integer operations
at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.
8. The typical maximum OVDD value resulted from the MPC8240 operating at the fastest frequency combination of
66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and
zeros to PCI memory.
9. The typical maximum GVDD value resulted from the MPC8240 operating at the fastest frequency combination of
66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and
zeros on 64-bit boundaries to local memory.
Table 18. MPC8240 Microprocessor PLL Configurations
Ref.
No.
PLL_
CFG
[0:4] 2
CPU 1
HID1[0:4]
250-MHz Part 8, 9
Ratios 3, 4
PCI Clock Input
(PCI_SYNC_IN)
Range (MHz)
Peripheral
Logic/Mem
Bus Clock Range
(MHz)
CPU Clock
Range
(MHz)
PCI to Mem
(Mem VCO)
Multiplier
Mem to CPU
(CPU VCO)
Multiplier
0
00000
00110
25–33
75–100
188–250
3 (6)
2.5 (5)
1
00001
11000
25–27
75–83
225–250
3 (6)
2
00010
00101
50–56 5
50–56
100–112
1 (4)
2 (8)
3
00011
00101
Bypass
2 (8)
4
00100
00101
25–28 5
50–56
100–113
2 (8)
Table 5. Preliminary Power Consumption (continued)
Mode
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Unit
Notes
33/66/233
33/83/250
33/100/200
33/100/250
66/100/200
66/100/250
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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