參數(shù)資料
型號(hào): XPC850DECVR66BU
廠商: Freescale Semiconductor
文件頁數(shù): 41/72頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 66MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
46
Freescale Semiconductor
CPM Electrical Characteristics
Figure 44. CPM General-Purpose Timers Timing Diagram
8.5
Serial Interface AC Electrical Specifications
Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49.
Table 17. SI Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
70
L1RCLK, L1TCLK frequency (DSC = 0) 1, 2
SYNCCLK/2.
5
MHz
71
L1RCLK, L1TCLK width low (DSC = 0) 2
P + 10
ns
71a
L1RCLK, L1TCLK width high (DSC = 0) 3
P + 10
ns
72
L1TXD, L1ST
n, L1RQ, L1xCLKO rise/fall time
15.00
ns
73
L1RSYNC, L1TSYNC valid to L1xCLK edge Edge
(SYNC setup time)
20.00
ns
74
L1xCLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
35.00
ns
75
L1RSYNC, L1TSYNC rise/fall time
15.00
ns
76
L1RXD valid to L1xCLK edge (L1RXD setup time)
17.00
ns
77
L1xCLK edge to L1RXD invalid (L1RXD hold time)
13.00
ns
78
L1xCLK edge to L1ST
n valid 4
10.00
45.00
ns
78A
L1SYNC valid to L1ST
n valid
10.00
45.00
ns
79
L1xCLK edge to L1ST
n invalid
10.00
45.00
ns
80
L1xCLK edge to L1TXD valid
10.00
55.00
ns
80A
L1TSYNC valid to L1TXD valid 4
10.00
55.00
ns
81
L1xCLK edge to L1TXD high impedance
0.00
42.00
ns
CLKOUT
TIN/TGATE
(Input)
TOUT
(Output)
64
65
61
62
63
61
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