參數(shù)資料
型號: XPC850ZT66BU
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 33/76頁
文件大小: 825K
代理商: XPC850ZT66BU
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
33
Layout Practices
Figure 6-20 provides the timing for the asynchronous external master memory access
controlled by the GPCM.
Figure 6-20. Asynchronous External Master Memory Access Timing (GPCM
Controlled—ACS = 00)
Figure 6-21 provides the timing for the asynchronous external master control signals
negation.
Figure 6-21. Asynchronous External Master—Control Signals Negation Timing
Table 6-7 provides interrupt timing for the MPC850.
Table 6-7. Interrupt Timing
Num
Characteristic
1
50 MHz
66MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
I39
IRQx valid to CLKOUT rising edge (set up time)
6.00
6.00
6.00
ns
I40
IRQx hold time after CLKOUT.
2.00
2.00
2.00
ns
I41
IRQx pulse width low
3.00
3.00
3.00
ns
I42
IRQx pulse width high
3.00
3.00
3.00
ns
I43
IRQx edge-to-edge time
80.00
121.0
100.0
ns
CLKOUT
AS
A[6:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
B43
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