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參數(shù)資料
| 型號(hào)： | XQ1701L-SO20N |
| 英文描述： | Configuration EPROM |
| 中文描述： | 配置存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | XQ1701L-SO20N |
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R
Instruction Register
The Instruction Register (IR) for the XQ(R)18V04 is eight
bits wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instruction register from TDI. The detailed
composition of the instruction capture pattern is illustrated
in
Figure 3
.
The ISP Status field, IR(4), contains logic "1" if the device is
currently in ISP mode; otherwise, it will contain logic "0".
The Security field, IR(3), will contain logic "1" if the device
has been programmed with the security option turned on;
otherwise, it will contain logic "0".
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
on the XQ(R)18V00 has two register stages that contribute
to the boundary-scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI con-
trols and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction. The IDCODE is avail-
able to any other system component via JTAG.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (50h for XQ(R)18V04 family)
a = the ISP PROM product ID (26h for the XQ(R)18V04)
c = the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as
logic "1" as defined by IEEE Std. 1149.1
Table 4
lists the IDCODE register values for the
XQ(R)18V00 devices. 0
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply informa-
tion about the device
’
s programmed contents. By using the
USERCODE instruction, a user-programmable identifica-
tion code can be shifted out for examination. This code is
loaded into the USERCODE register during programming of
the XQ(R)18V04 device. If the device is blank or was not
loaded during programming, the USERCODE register will
contain FFFFFFFFh.
XQ(R)18V04 TAP Characteristics
The XQ(R)18V04 family performs both in-system program-
ming and IEEE 1149.1 boundary-scan (JTAG) testing via a
single 4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. The AC characteristics of the
XQ(R)18V04 TAP are described as follows.
TAP Timing
Figure 4
shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
IR[7:5]
IR[4]
IR[3]
IR[2]
IR[1:0]
TDI->
0 0 0
ISP
Status
Security
0
0 1
->TDO
Notes:
1.
IR(1:0) = 01 is specified by IEEE Std. 1149.1
Figure 3:
Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Table 4:
IDCODES Assigned to XQ(R)18V04 Devices
ISP-PROM
IDCODE
XQ(R)18V04
05026093h
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