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| 型號(hào)： | XQ4000EXSERIES |
| 元件分類(lèi)： | FPGA |
| 英文描述： | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| 中文描述： | QPRO XQ4000E/EX QML第高可靠性的FPGA |
| 文件頁(yè)數(shù)： | 23/36頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | XQ4000EXSERIES |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
Symbol
Write Operation
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
Notes:
1.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Single Port RAM
Size
-4
Units
Min
Max
Address write cycle time (clock K period)
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
11.0
11.0
5.5
5.5
2.7
2.6
0
0
2.4
2.9
0
0
2.3
2.1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
8.2
10.1
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Write Operation
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
Notes:
1.
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual Port RAM
Size
(1)
-4
Units
Min
Max
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
11.0
5.5
3.1
0
2.9
0
2.1
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
9.4
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