- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372927 > XQ4010E-4CB196N (Xilinx, Inc.) QPRO XQ4000E/EX QML High-Reliability FPGAs PDF資料下載
參數(shù)資料
| 型號(hào)： | XQ4010E-4CB196N |
| 廠商： | Xilinx, Inc. |
| 元件分類： | FPGA |
| 英文描述： | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| 中文描述： | QPRO XQ4000E/EX QML第高可靠性的FPGA |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 304K |
| 代理商： | XQ4010E-4CB196N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
Symbol
T
ICKOF
(Max)
Description
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-3
-
-4
Units
ns
ns
ns
ns
Global clock to output (fast) using OFF
14.0
16.0
16.5
17.0
10.9
11.0
-
T
ICKO
(Max)
Global clock to output (slew-limited) using OFF
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
18.0
20.0
20.5
21.0
ns
ns
ns
ns
14.9
15.0
-
T
PSUF
(Min)
Input setup time, using IFF (no delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
2.0
1.0
0.5
0
ns
ns
ns
ns
0.2
0
-
T
PHF
(Min)
Input hold time, using IFF (no delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
4.6
6.0
7.0
8.0
ns
ns
ns
ns
5.5
6.5
-
T
PSU
(Min)
Input setup time, using IFF (with delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
8.5
8.5
8.5
9.5
ns
ns
ns
ns
7.0
7.0
-
T
PH
(Min)
Input hold time, using IFF (with delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
0
0
-
0
0
0
0
ns
ns
ns
ns
Notes:
1.
2.
OFF = Output Flip-Flop
IFF = Input Flip-Flop or Latch
OFF
T
PG
Global Clock-to-Output Delay
DS021_04_060100
OFF
T
PG
Global Clock-to-Output Delay
DS021_04_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ4010E-4HQ191M | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-4HQ191N | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-4PG191M | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-4PG191N | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4013E | QPRO XQ4000E/EX QML High-Reliability FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4010E-4HQ191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-4HQ191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-4HQ196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4010E-4HQ196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4010E-4PG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。