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參數資料
| 型號： | XQ4010E |
| 廠商： | Xilinx, Inc. |
| 元件分類： | FPGA |
| 英文描述： | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| 中文描述： | QPRO XQ4000E/EX QML第高可靠性的FPGA |
| 文件頁數： | 13/36頁 |
| 文件大小： | 304K |
| 代理商： | XQ4010E |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
Symbol
T
ICKOF
(Max)
Description
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-3
-
-4
Units
ns
ns
ns
ns
Global clock to output (fast) using OFF
14.0
16.0
16.5
17.0
10.9
11.0
-
T
ICKO
(Max)
Global clock to output (slew-limited) using OFF
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
18.0
20.0
20.5
21.0
ns
ns
ns
ns
14.9
15.0
-
T
PSUF
(Min)
Input setup time, using IFF (no delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
2.0
1.0
0.5
0
ns
ns
ns
ns
0.2
0
-
T
PHF
(Min)
Input hold time, using IFF (no delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
4.6
6.0
7.0
8.0
ns
ns
ns
ns
5.5
6.5
-
T
PSU
(Min)
Input setup time, using IFF (with delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
8.5
8.5
8.5
9.5
ns
ns
ns
ns
7.0
7.0
-
T
PH
(Min)
Input hold time, using IFF (with delay)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-
0
0
-
0
0
0
0
ns
ns
ns
ns
Notes:
1.
2.
OFF = Output Flip-Flop
IFF = Input Flip-Flop or Latch
OFF
T
PG
Global Clock-to-Output Delay
DS021_04_060100
OFF
T
PG
Global Clock-to-Output Delay
DS021_04_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
T
PG
D
Input
Setup
and Hold
Time
DS021_05_060100
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相關代理商/技術參數 |
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| XQ4010E-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-3BG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4010E-3BG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4010E-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4010E-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
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