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| 型號(hào)： | XQ4028EX |
| 廠商： | Xilinx, Inc. |
| 元件分類(lèi)： | FPGA |
| 英文描述： | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| 中文描述： | QPRO XQ4000E/EX QML第高可靠性的FPGA |
| 文件頁(yè)數(shù)： | 27/36頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | XQ4028EX |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778XQ4028EX Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000EX
devices unless otherwise noted.
XQ4028EX Output Flip-Flop, Clock to Out
(1,2)
XQ4028EX Output Mux, Clock to Out
(1,2)
XQ4028EX Output Level and Slew Rate Adjustments
The following table must be used to adjust output parameters and output switching characteristics.
Symbol
Description
-4
Units
Max
T
ICKOF
T
ICKEOF
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at TTL threshold with 50 pF external capacitive load.
3.
OFF = Output Flip-Flop
Global low skew clock to output using OFF
(3)
Global early clock to output using OFF
(3)
16.6
ns
13.1
ns
Symbol
Description
-4
Units
Max
T
PFPF
T
PEFPF
Global low skew clock to TTL output (fast) using OMUX
3)
Global early clock to TTL output (fast) using OMUXF
(3)
15.9
ns
12.4
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see graph below.
OMUX = Output MUX
2.
3.
Symbol
Description
-4
Units
Max
T
TTLOF
T
TTLO
T
CMOSOF
T
CMOSO
For TTL output FAST add
0
ns
For TTL output SLOW add
2.9
ns
For CMOS FAST output add
1.0
ns
For CMOS SLOW output add
3.6
ns
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