參數(shù)資料
型號: XR-2207M
廠商: EXAR CORP
元件分類: XO, clock
英文描述: Voltage-Controlled Oscillator
中文描述: VCO, 0.00000001 MHz - 1 MHz
封裝: 0.300 INCH, CERAMIC, DIP-14
文件頁數(shù): 10/24頁
文件大?。?/td> 248K
代理商: XR-2207M
XR-2207
10
Rev. 2.02
Binary Keying Inputs (Pins 8 and 9)
The logic levels applied to the two binary keying inputs
allow the selection of four different oscillator frequencies.
The internal impedance at these pins is approximately
5k
. Keying voltages, which are referenced to pin 10, are
< 1.4 V for “zero” and > 3V for “one” logic levels. Table 1
relates binary keying input logic levels, and selected
timing pins to oscillator output frequency for each of the
four possible cases.
Figure 12shows the oscillator control mechanism in
greater detail. Timing pins 4, 5, 6 and 7 correspond to the
emitters of switching transistor pairs T1, T2, T3, and T4
respectively, which are internal to the integrated circuit.
The current switches, and corresponding timing
terminals, are activated by external logic signals applied
to pins 8 and 9.
Logic Level
Selected
Timing Pins
Frequency
Pin 8
Pin 9
0
0
6
f
1
0
1
6 and 7
f
1
+ f
1
f
2
f
2
+ f
2
1
0
5
1
1
4 and 5
Table 1. Logic Table for Binary Keying Controls
Definitions:
f
1
1
R
3
C
f
1
1
R
4
C
f
2
1
R
2
C
f
2
1
R
1
C
Logic Levels: 0 = Ground, 1
Note
For single supply operation, logic levels are referenced to
voltage at pin 10
3V
2
Timing Capacitor
C
IT/2
3
IT/2
Ib
1
T4
T3
T2
T1
Binary
Keying
Controls
8
A
10
V
6
7
I3
I4
4
5
I1
I2
9
B
R2
R1
R3
R4
V
EE
12
Figure 12. Simplified Schematic of Frequency
Control Mechanism
V
CC
Squarewave Output (Pin 13)
The squarewave output at pin 13 is an “open-collector”
stage capable of sinking up to 20mA of load current. R
L
serves as a pull-up load resistor for this output.
Recommended values for R
L
range from 1k
to 100k
.
Triangle Output (Pin 14)
The output at pin 14 is a triangle wave with a peak swing of
approximately one-half of the total supply voltage. Pin 14
has a 10
output impedance and is internally protected
against short circuits.
MODES OF OPERATION
Split Supply Operation
Figure 13is the recommended configuration for split
supply operation. The circuit operates with supply
voltages ranging from
4V to
occurs with
6V supplies. For operation with unequal
supply voltages, see Figure 5
With the generalized circuit of Figure 13A the frequency
of operation is determined by the timing capacitor, C, and
the activated timing resistors (R
1
through R
4
). The timing
resistors are activated by the logic signals at the binary
13V. Minimum drift
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