
XR-T5683A
2
Rev. 2.01
PIN CONFIGURATION
18 Lead PDIP (0.300”)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TV
CC
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RPOS
RNEG
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RGND
RCLK
RV
CC
18 Lead SOIC (JEDEC, 0.300”)
18
1
10
9
2
3
4
5
6
7
15
14
13
12
11
17
16
8
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RGND
RCLK
RV
CC
TV
CC
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RPOS
RNEG
PIN DESCRIPTION
Pin #
Symbol
Type
Description
Peak Detector Capacitor.
This pin should be connected to a 0.1
μ
F capacitor.
Receive Analog Input Positive.
Line analog input.
1
PDC
2
RXDATA+
I
3
RXDATA-
I
Receive Analog Input Negative.
Line analog input.
4
TE
O
Tank Excitation Output.
This output connects to one side of the tank circuitry.
5
BIAS
O
Bias.
This output is to be connected to the center tap of the receive transformer.
6
TANK BIAS
O
Tank Bias.
The tank circuitry is biased via this output.
7
RGND
Receiver Ground.
To minimize ground interference a separate pin is used to ground the
receive section.
Recovered Receive Clock.
Recovered clock signal to the terminal equipment.
8
RCLK
O
9
RV
CC
RNEG
Receive Supply Voltage.
5V supply voltage to the receive section.
10
O
Receive Negative Data.
Negative pulse data output to the terminal equipment (active low).
11
RPOS
O
Receive Positive Data.
Positive pulse data output to the terminal equipment (active low).
12
TNEG
I
Transmit Negative Data.
TNEG is valid while TCLK is high.
13
TXDATA+
O
Transmit Positive Output.
Transmit bipolar signal is driven to the line via a transformer.
14
TGND
Transmit Ground.
15
TXDATA-
O
Transmit Negative Output.
Transmit bipolar signal is driven to the line via a transformer.
16
TCLK
I
Transmit Clock.
Timing element for TPOS and TNEG.
17
TPOS
I
Transmit Positive Data.
TPOS is valid while TCLK is high.
18
TV
CC
Transmit Supply Voltage.
5V supply voltage to the transmit section.