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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | XR16C2850CJTR-F |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/51闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC UART FIFO 128B 44PLCC |
| 妯欐簴鍖呰锛� | 500 |
| 鐗归粸锛� | * |
| 閫氶亾鏁�(sh霉)锛� | 2锛孌UART |
| FIFO's锛� | 128 瀛楃瘈(ji茅) |
| 瑕�(gu墨)绋嬶細 | RS232锛孯S485 |
| 闆绘簮闆诲锛� | 2.97 V ~ 5.5 V |
| 甯惰嚜鍕曟祦閲忔帶鍒跺姛鑳斤細 | 鏄� |
| 甯禝rDA 绶ㄧ⒓鍣�/瑙ｇ⒓鍣細 | 鏄� |
| 甯舵晠闅滃暉鍕曚綅妾㈡脯鍔熻兘锛� | 鏄� |
| 甯惰(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒跺姛鑳斤細 | 鏄� |
| 甯禖MOS锛� | 鏄� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-PLCC锛�16.59x16.59锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
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xr
XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
11
Typical oscillator connections are shown in Figure 4. For further reading on oscillator circuit please see
application note DAN108 on EXAR鈥檚 web site.
2.9
Programmable Baud Rate Generator
A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of
up to 24 MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2
pin (as shown in Figure 5) it can extend its operation up to 50 MHz (3.125 Mbps serial data rate and 16X
sampling) at room temperature and 5.0V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
Each UART also has their own prescaler along with the BRG. The prescaler is controlled by CLKSEL hardware
pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or
external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the prescaler
goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 -1) to
obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for
data bit shifting and receiver for data sampling.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode to double the operating data rate. When using a non-standard data rate crystal or
external clock, the divisor value can be calculated for DLL/DLM with the following equation.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
2K
XTAL1
XTAL2
R1
VCC
External Clock
vcc
gnd
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XR16C2850CM | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪: |
| XR16C2850CM-0A-EB | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 Supports C2850 48 ld TQFP, ISA Interface RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| XR16C2850CM-0B-EB | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 Supports C2850 48 ld TQFP, PCI Interface RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| XR16C2850CM48 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850CM-F | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 2.97V-5.5V 128B FIFO temp 0C to 70C; UART RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
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