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參數(shù)資料
| 型號： | XR16C2850CP |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| 中文描述： | 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/43頁 |
| 文件大?。?/td> | 611K |
| 代理商： | XR16C2850CP |
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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
6
1.0
The XR16C2850 (2850) integrates the functions of 2
enhanced 16C550 Universal Asynchrounous Receiv-
er and Transmitter (UART). Each UART is indepen-
dently controlled having its own set of device configu-
ration registers. The configuration registers set is
16550 UART compatible for control, status and data
transfer. Additionally, each UART channel has 128-
bytes of transmit and receive FIFOs, automatic RTS/
CTS hardware flow control with hysteresis control,
automatic Xon/Xoff and special character software
flow control, programmable transmit and receive
FIFO trigger levels, FIFO level counters, infrared en-
coder and decoder (IrDA ver 1.0), programmable
baud rate generator with a prescaler of divide by 1 or
4, and data rate up to 6.25 Mbps with 8X sampling
clock rate or 3.125Mbps in the 16X rate. The
XR16C2850 is a 5V and 3.3V device. The 2850 is
fabricated with an advanced CMOS process.
Enhanced Features
The 2850 DUART provides a solution that supports
128 bytes of transmit and receive FIFO memory, in-
stead of 64 bytes provided in the XR16L2750 and 16
bytes in the ST16C2550, or one byte in the
ST16C2450. The 2850 is designed to work with high
performance data communication systems, that re-
quire fast data processing time. Increased perfor-
mance is realized in the 2850 by the larger transmit
and receive FIFOs, FIFO trigger level control, FIFO
level counters and automatic flow control mecha-
nism. This allows the external processor to handle
more networking tasks within a given time. For exam-
ple, the ST16C2550 with a 16 byte FIFO, unloads 16
bytes of receive data in 1.53 ms (This example uses a
character length of 11 bits, including start/stop bits at
115.2Kbps). This means the external CPU will have
to service the receive FIFO at 1.53 ms intervals. How-
ever with the 128 byte FIFO in the 2850, the data
buffer will not require unloading/loading for 12.2 ms.
This increases the service interval giving the external
CPU additional time for other applications and reduc-
ing the overall UART interrupt servicing time. In addi-
PRODUCT DESCRIPTION
tion, the programmable FIFO level trigger interrupt
and automatic hardware/software flow control is
uniquely provided for maximum data throughput per-
formance especially when operating in a multi-chan-
nel system. The combination of the above greatly re-
duces the CPU’s bandwidth requirement, increases
performance, and reduces power consumption.
The 2850 supports a half-duplex output direction con-
trol signaling pin, RTS# A/B, to enable and disable
the external RS-485 transceiver operation. It auto-
matically switches the logic state of the output pin to
the receive state after the last stop-bit of the last char-
acter has been shifted out of the transmitter. After re-
ceiving, the logic state of the output pin switches back
to the transmit state when a data byte is loaded in the
transmitter. The auto RS-485 direction control pin is
not activated after reset. To activate the direction con-
trol function, user has to set FCTR Bit-3 to “1”. This
pin is normally high for receive state, low for transmit
state.
Data Rate
The 2850 is capable of operation up to 3.125Mbps at
5V with 16x internal sampling clock rate, and
6.25Mbps at 5V with 8x sampling clock rate (available
only on the 48-pin package). The device can operate
with an external 24 MHz crystal on pins XTAL1 and
XTAL2, or external clock source of up to 50 MHz on
XTAL1 pin. With a typical crystal of 14.7464 MHz and
through a software option, the user can set the pres-
caler bit for data rates of up to 1.84Mbps.
The rich feature set of the 2850 is available through
the internal registers. Automatic hardware/software
flow control, selectable transmit and receive FIFO
trigger levels, selectable TX and RX baud rates, infra-
red encoder/decoder interface, modem interface con-
trols, and a sleep mode are all standard features.
Following a power on reset or an external reset, the
2850 is software compatible with previous generation
of UARTs, 16C450, 16C550 and 16C650Aas well as
the 16C850.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C2850IJ | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850IM | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850IP | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2852 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852CJ | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850CP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ | 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
| XR16C2850IJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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