參數(shù)資料
型號: XR16C2850IJ44
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 20/43頁
文件大?。?/td> 611K
代理商: XR16C2850IJ44
á
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
20
4.0
4.1
INTERNAL REGISTER DESCRIPTIONS
R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
-
O
NLY
See “Receiver” on page 12.
4.2
T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
-
O
NLY
See “Transmitter” on page 11.
4.3
I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/
W
RITE
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode
Operation
When the receive FIFO (FCR BIT-0 = 1) and receive
interrupts (IER BIT-0 = 1) are enabled, the RHR inter-
rupts (see ISR bits 2 and 3) status will reflect the fol-
lowing:
A.
The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
C.
The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the
FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled
Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; re-
setting IER bits 0-3 enables the XR16C2850 in the
FIFO polled mode of operation. Since the receiver
and transmitter have separate bits in the LSR either
or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR
or
RX
FIFO.
B.
LSR BIT-1 indicates an overrun error has oc-
C.
LSR BIT 2-4 provides the type of receive data er-
rors encountered for the data byte in RHR, if any.
D.
LSR BIT-5 indicates THR is empty.
E.
LSR BIT-6 indicates when both the transmit FIFO
and TSR are empty.
F.
LSR BIT-7 indicates a data error in at least one
character in the RX FIFO.
Enhanced Registers
0 0 0
TRG
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0
X
BF
0 0 0
FC
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
FCTR
RD/WR
RX/TX
Mode
SCPAD
Swap
Trig
Table
Bit-1
Trig
Table
Bit-0
Auto
RS485
Direction
Control
RX IR
Input
Inv.
Auto
RTS
Hyst Bit-
1
Auto
RTS
Hyst Bit-
0
0 1 0
EFR
RD/WR Auto CTS
Enable
Auto RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
1 0 0
XON1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1
XON2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0
XOFF1 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1
XOFF2 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
T
ABLE
8: INTERNAL REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1
A
DDRESS
A2-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
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