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參數(shù)資料
| 型號： | XR16C2850IJTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 128B 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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xr
XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
27
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level. Table 10 shows the complete selections. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER
TABLE
FCTR
BIT-5
FCTR
BIT-4
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
Table-A
0
1
0
1
0
1
0
1 (default)
4
8
14
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580
Table-B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
24
28
16
8
24
30
16C650A
Table-C
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
16C654
Table-D
1
X
Programmable
via TRG
register.
FCTR[7] = 0.
Programmable
via TRG
register.
FCTR[7] = 1.
16L2752, 16L2750,
16C2852, 16C850,
16C854, 16C864
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2850IM48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IM-F | 功能描述:UART 接口集成電路 2.97V-5.5V 128B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IMTR-F | 制造商:Exar Corporation 功能描述:XR16C2850IMTR-F |
| XR16C2850IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
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