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參數(shù)資料
| 型號(hào)： | XR16C2850IP |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| 中文描述： | 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 23/43頁 |
| 文件大小： | 611K |
| 代理商： | XR16C2850IP |
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XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
23
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY#
pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO.
The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the se-
lected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last
re-load. Table 10
below shows the selections. EFR
bit-4 must be set to ‘1’ before these bits can be ac-
cessed. Note that the receiver and the transmitter
cannot use different trigger tables. Whichever selec-
tion is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receive FIFO. The UART will issue a receive interrupt
when the number of the characters in the FIFO cross-
es the trigger level. Table 10 shows the complete se-
lections.
N
OTE
:
The receiver and the transmitter cannot use different
trigger tables. Whichever selection is made last applies to
both the RX and TX side.
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCTR
B
IT
-5
FCTR
B
IT
-4
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
0
0
1
1
0
1
0
1
0
0
1 (default)
4
8
14
1 (default)
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
24
28
16
8
24
30
Table-B. 16C650A compatible.
1
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
Table-C. 16C654 compatible.
1
1
X
X
X
X
Programmable
via TRG
register.
FCTR[7] = 0.
Programmable
via TRG
register.
FCTR[7] = 1.
Table-D. 16C850, 16L2752,
16L2750, 16C2852, 16C854,
16C864, 16C872 compatible.
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| XR16C850CJ | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850IP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852CJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C2852CJ-0A-EB | 功能描述:UART 接口集成電路 Supports C2852 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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