參數(shù)資料
型號(hào): XR16C2852CJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 24/42頁
文件大小: 574K
代理商: XR16C2852CJ
á
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
24
4.7
The Line Control Register is used to specify the asyn-
chronous data communication format. The word or
character length, the number of stop bits, and the par-
ity are selected by writing the appropriate bits in this
register.
LCR[1-0]: TX and RX Word Length Select
These two bits specify the word length to be transmit-
ted or received.
L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in con-
junction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See Table 11 for parity selection
summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the trans-
mission while the receiver checks for parity error of
the data character received.
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCTR
B
IT
-5
FCTR
B
IT
-4
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
0
0
1
1
0
1
0
1
0
0
1 (default)
4
8
14
1 (default)
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
24
28
16
8
24
30
Table-B. 16C650A compatible.
1
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
Table-C. 16C654 compatible.
1
1
X
X
X
X
Programmable
via TRG
register.
FCTR[7] = 0.
Programmable
via TRG
register.
FCTR[7] = 1.
Table-D. 16C850, 16L2750,
16C2850, 16L2752, 16C854,
16C864, 16C872 compatible.
BIT-1
BIT-0
W
ORD
LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
BIT-2
W
ORD
LENGTH
S
TOP
BIT
LENGTH
(B
IT
TIME
(
S
))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
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PDF描述
XR16C2852IJ 3.3V AND 5V DUART WITH 128-BYTE FIFO
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