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參數(shù)資料
| 型號(hào)： | XR16C850CP |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| 中文描述： | 1 CHANNEL(S), 2.25M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 28/55頁 |
| 文件大?。?/td> | 331K |
| 代理商： | XR16C850CP |
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XR16C850
28
Rev. 1.20
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the FIFO counter and resets the
pointers logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing
the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condition)
Logic 1 = Set DMA mode “1.”
Transmit operation n mode “0”:
When the 850 is in the ST16C450 mode (FIFOs dis-
abled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs
enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and
when there are no characters in the transmit FIFO or
transmit holding register, the -TXRDY pin will be a logic
0. Once active the -TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding
register.
Receive operation n mode “0”:
When the 850 is in mode “0” (FCR bit-0 = logic 0) or in
the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic
0) and there is at least one character in the receive FIFO,
the -RXRDY pin will be a logic 0. Once active the -
RXRDY pin will go to a logic 1 when there are no more
characters in the receiver.
Transmit operation n mode “1”:
When the 850 is in FIFO mode ( FCR bit-0 = logic 1, FCR
bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when
the transmit FIFO is completely full. It will be a logic 0
if one or more FIFO locations are empty.
Receive operation n mode “1”:
When the 850 is in FIFO mode (FCR bit-0 = logic 1, FCR
bit-3 = logic 1) and the trigger level has been reached,
or a Receive Time Out has occurred, the -RXRDY pin will
go to a logic 0. Once activated, it will go to a logic 1 after
there are no more characters in the FIFO.
FCR BIT 4-5: (logic 0 or cleared s he default condition,
TX trigger level = none)
The XR16C850 provides 4 user selectable trigger evels,
The FCTR Bits 4-5 selects one of the following tables.
These bits are used to set the trigger level for the
transmit FIFO interrupt. The XR16C850 will issue a
transmit empty interrupt when the number of characters
in FIFO drops below the selected trigger level.
TRIGGER TABLE-A (Transmit)
“Default setting after reset, ST16C550 mode”
BIT-5
BIT-4
FIFO trigger level
X
X
None
TRIGGER TABLE-B (Transmit)
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
16
8
24
30
TRIGGER TABLE-C (Transmit)
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
32
56
TRIGGER TABLE-D (Transmit)
BIT-5
BIT-4
FIFO trigger level
X
X
User programmable
Trigger evels
FCR BIT 6-7: (logic 0 or cleared s he default condition,
RX trigger evel =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The interrupt will trigger again
when RX data is unloaded below the threshold and
incoming data fills it back up to the trigger level. The
FCTR Bits 4-5 selects one of the following tables.
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相關(guān)代理商/技術(shù)參數(shù) |
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| XR16C850CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 128-BYTE FIFO |
| XR16C850IJ-F | 功能描述:UART 接口集成電路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850IJTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC T/R |
| XR16C850IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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