參數(shù)資料
型號: XR16L2450IM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART
中文描述: 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 13/30頁
文件大?。?/td> 511K
代理商: XR16L2450IM
xr
REV. 1.1.0
XR16L2450
2.25V TO 5.5V DUART
13
.
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
See “Receiver” on page 10.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 9.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
Receive Holding Register (RHR) - Read- Only
T
ABLE
5: INTERNAL REGISTERS DESCRIPTION
A
DDRESS
A2-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
16C450 Compatible Registers
0 0 0
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
0 0 0
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
IER
RD/WR
0
0
0
0
Modem
Stat.
Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
0 1 0
ISR
RD
0
0
0
0
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
0 1 1
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0
MCR
RD/WR
0
0
0
Internal
Loop-
back
Enable
OP2#/
INT
Output
Enable
Rsrvd
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
1 0 1
LSR
RD
0
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Fram-
ing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
1 1 1
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 1
0 0 1
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 0
DREV
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
DLL=0x00
DLM=0x00
0 0 1
DVID
RD
0
0
0
0
0
0
1
0
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