參數(shù)資料
型號(hào): XR16L2750IJ
廠商: EXAR CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 5/49頁(yè)
文件大?。?/td> 602K
代理商: XR16L2750IJ
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
á
5
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
RXB
10
4
I
UART channel B Receive Data or infrared receive data. Normal receive
data input must idle at logic 1 condition. The infrared receiver pulses
typically idles at logic 0 but can be inverted by software control prior
going in to the decoder, see MCR[6] and FCTR[2]. If this pin is not
used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSB#
27
22
O
UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto
RS485 half-duplex direction control, see FCTR[3] and EMSR[3].
CTSB#
28
23
I
UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
DTRB#
38
35
O
UART channel B Data-Terminal-Ready (active low) or general purpose
output.
If it is not used, leave it unconnected.
DSRB#
25
20
I
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
CDB#
21
16
I
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
RIB#
26
21
I
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
OP2B#
15
9
O
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. See MCR[3]. This output should not be used as a general
output else it will disturb the INTB output functionality.
ANCILLARY SIGNALS
XTAL1
18
13
I
Crystal or external clock input. Caution: this input is not 5V tolerant.
XTAL2
19
14
O
Crystal or buffered clock output.
RESET
39
36
I
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period (see External Reset Conditions).
VCC
44
42
Pwr
2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V toler-
ant.
GND
22
17
Pwr
Power supply common, ground.
N.C.
none
12, 24, 25,
37
No Connection. These pins are open, but typically, should be con-
nected to GND for good design practice.
Pin Description
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
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