參數(shù)資料
型號(hào)： XR16L2750IM
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述： 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 7/49頁(yè)
文件大?。?/td> 602K
代理商： XR16L2750IM
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
á
7
2.0
FUNCTIONAL DESCRIPTIONS
2.1
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2750 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
Figure 3
.
CPU Interface
2.2
The 2750 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 2750 is operating
at 2.5V, its V
OH
may not be high enough to meet the requirements of the V
IH
of a CPU or a serial transceiver
that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
Table 16
). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.4
Device Identification and Revision
The XR16L2750 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the
XR16L2750 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the user to
select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART.
5-Volt Tolerant Inputs
F
IGURE
3. XR16L2750 D
ATA
B
US
I
NTERCONNECTIONS
VCC
VCC
OP2A#
DSRA#
CDA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
OP2B#
DSRB#
CDB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
D0
D4
A0
A1
A2
CSA#
CSB#
D0
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYB#
TXRDYA#
RXRDYA#
TXRDYB#
TXRDYA#
RXRDYB#
RXRDYB#
UART_RESET
RESET
Serial Interface of
RS-232, RS-485
Serial Interface of
RS-232, RS-485
2750int
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