參數(shù)資料
型號(hào)： XR16L2752IJ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述： 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 49/49頁(yè)
文件大?。?/td> 619K
代理商： XR16L2752IJ
xr
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.1.0
II
4.0 INTERNAL Register descriptions ........................................................................................ 22
4.1 R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
- O
NLY
........................................................................... 22
4.2 T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
-O
NLY
......................................................................... 22
4.3 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
.......................................................................... 22
4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 23
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 23
4.4 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-O
NLY
............................................................................ 24
4.4.1 Interrupt Generation:................................................................................................................................ 24
4.4.2 Interrupt Clearing: .................................................................................................................................... 24
4.5 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
-O
NLY
............................................................................... 25
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................................................................... 25
4.6 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
................................................................................ 27
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
T
ABLE
AND
L
EVEL
S
ELECTION
.................................................................................. 27
T
ABLE
11: P
ARITY
SELECTION
................................................................................................................................................................ 28
4.7 A
LTERNATE
F
UNCTION
R
EGISTER
(AFR) - R
EAD
/W
RITE
..................................................................... 29
4.8 M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
ENERAL
P
URPOSE
O
UTPUTS
C
ONTROL
- R
EAD
/W
RITE
....... 29
4.9 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
..................................................................................... 30
4.10 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
............................................................................. 31
4.11 S
CRATCH
P
AD
R
EGISTER
(SPR) - R
EAD
/W
RITE
............................................................................... 32
4.12 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR) ................................................................................. 32
T
ABLE
12: S
CRATCHPAD
S
WAP
S
ELECTION
............................................................................................................................................ 32
4.13 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
.................................................................................. 33
T
ABLE
13: RTS H
YSTERESIS
L
EVELS
.................................................................................................................................................... 33
4.14 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
.............................................. 34
4.15 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
................................................................. 34
4.16 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
......................................................................... 34
4.17 T
RIGGER
L
EVEL
R
EGISTER
(TRG) - W
RITE
-O
NLY
............................................................................ 34
4.18 RX/TX FIFO L
EVEL
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
.............................................................. 34
4.19 F
EATURE
C
ONTROL
R
EGISTER
(FCTR) - R
EAD
/W
RITE
..................................................................... 34
T
ABLE
14: T
RIGGER
T
ABLE
S
ELECT
....................................................................................................................................................... 35
T
ABLE
15: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
............................................................................................................................... 36
4.20 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1, XOFF2, XON1, XON2) - R
EAD
/W
RITE
............... 37
T
ABLE
16: UART RESET CONDITIONS FOR CHANNEL A AND B................................................................................................... 38
ABSOLUTE MAXIMUM RATINGS ..................................................................................39
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)39
ELECTRICAL CHARACTERISTICS................................................................................39
DC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................39
AC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................40
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25-5.5V, ......... 40
70 pF load where applicable .............................................................................................................................. 40
F
IGURE
14. C
LOCK
T
IMING
.................................................................................................................................................................... 41
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A & B......................................................................................................... 41
F
IGURE
16. D
ATA
B
US
R
EAD
T
IMING
..................................................................................................................................................... 42
F
IGURE
17. D
ATA
B
US
W
RITE
T
IMING
.................................................................................................................................................... 42
F
IGURE
18. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B................................................................. 43
F
IGURE
19. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B............................................................... 43
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A & B............................................... 44
F
IGURE
21. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A & B................................................ 44
F
IGURE
22. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A & B................................... 45
F
IGURE
23. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A & B.................................... 45
PACKAGE DIMENSIONS (44 PIN PLCC).......................................................................46
R
EVISION
H
ISTORY
....................................................................................................................................47
TABLE OF CONTENTS ................................................................................................................................. I
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