參數(shù)資料
型號(hào)： XR16L570IL24TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 9/47頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B 24QFN
標(biāo)準(zhǔn)包裝： 3,000
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 1.62 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 帶卷 (TR)
XR16L570
17
REV. 1.0.1
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.18
Sleep Mode with Wake-Up Interrupt and Power-Save Feature
The L570 supports low voltage system designs, hence, a sleep mode with wake-up interrupt and Power-Save
feature is included to reduce power consumption when the device is not actively used.
2.18.1
Sleep Mode
All of these conditions must be satisfied for the L570 to enter sleep mode:
■ no interrupts pending (ISR bit-0 = 1)
■ the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
■ sleep mode is enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RX input pin is idling at a logic 1
The L570 resumes normal operation by any of the following:
■ a receive data start bit transition (HIGH to LOW)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on the modem or general purpose serial input CTS#
If the L570 is awakened by any one of the above conditions, it issues an interrupt as soon as the oscillator
circuit is up and running and the device is ready to transmit/receive. This interrupt has the same encoding (bit-
0 of ISR register = 1) as "no interrupt pending" and will clear when the ISR register is read. This will show up in
the ISR register only if no other interrupts are enabled. The L570 will return to the sleep mode automatically
after all interrupting conditions have been serviced and cleared. If the L570 is awakened by the modem input
CTS#, a read to the MSR is required to reset the modem input. In any case, the sleep mode will not be entered
while an interrupt is pending. The L570 will stay in the sleep mode of operation until it is disabled by setting IER
bit-4 to a logic 0.
2.18.2
Power-Save Feature
If the address lines, data bus lines, IOW#, IOR#, CS# and modem input lines remain steady when the L570 is
in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 35. If the input lines are floating or are toggling while the L570 is in sleep mode, the
current can be up to 100 times more. If not using the Power-Save feature, an external buffer would be required
to keep the address and data bus lines from toggling or floating to achieve the low current. But if the Power-
Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an external buffer by
internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that
could cause wasteful power drain. The L570 enters Power-Save mode when this pin is connected to VCC and
the L570 is in sleep mode (see Sleep Mode section above).
Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:
■ a receive data start bit transition (HIGH to LOW) at the RX input or
■ a change of logic state on the modem or general purpose serial input CTS#
The L570 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem input
CTS#) and all interrupting conditions have been serviced and cleared. The L570 will stay in the Power-Save
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to
GND. The Power-Save feature is only available in the 24-QFN package only.
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