FIGURE 21. R
參數(shù)資料
型號(hào): XR16M554IJ-0B-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 31/46頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR XR16M554-B 68PLCC
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16M554/554D
37
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
Data in
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
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