參數(shù)資料
型號(hào)： XR16M580IB25TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 2/56頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B 25BGA
標(biāo)準(zhǔn)包裝： 2,500
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 25-WFBGA
供應(yīng)商設(shè)備封裝： 25-BGA（3x3）
包裝： 帶卷 (TR)
XR16M580
10
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs to their default state (see
Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device. Following a power-on reset or an external reset, the M580 is software compatible with previous
generation of UARTs, XR16L580 and ST16C550.
2.4
Internal Registers
The M580 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M580 offers enhanced feature registers (EFR, Xon1/
Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR and FC) that provide automatic RTS and CTS hardware flow control,
automatic Xon/Xoff software flow control, 9-bit (Multidrop) mode, auto RS-485 half duplex control, different
baud rate for TX and RX and fractional baud rate generator. All the register functions are discussed in full
2.5
INT Ouput
The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2
summarize the operating behavior for the transmitter and receiver. Also see Figure 22 through 25.
NOTE: The IRQ# pin requires a pull-up resistor for proper operation.
TABLE 1: INT PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
(16/68# = 1)
LOW = One byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
IRQ# Pin
(16/68# = 0)
HIGH = One byte in THR
LOW = THR empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
TABLE 2: INT PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
(16/68# = 1)
HIGH = One byte in RHR
LOW = RHR empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level or RX Data Timeout
IRQ# Pin
(16/68# = 0)
LOW = One byte in RHR
HIGH = RHR empty
HIGH = FIFO below trigger level
LOW = FIFO above trigger level or RX Data Timeout
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