參數(shù)資料
型號(hào)： XR16M654DIV64-F
廠商： Exar Corporation
文件頁數(shù)： 35/58頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B QUAD 64LQFP
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
XR16M654/654D
40
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.0
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.13
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 8.
4.14
FIFO Status Register (FSTAT) - Read/Write
This register is applicable only to the 100 pin QFP XR16M654. The FIFO Status Register provides a status
indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the
TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the
FSTAT register are placed on the data bus when the FSRS# pin (pin 76) is a logic 0. Also see FSRS# pin
description.
FSTAT[3:0]: TXRDY# A-D Status Bits
Please see Table 5 for the interpretation of the TXRDY# signals.
FSTAT[7:4]: RXRDY# A-D Status Bits
Please see Table 5 for the interpretation of the RXRDY# signals.
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XR16M654IJ-0B-EVB 功能描述:界面開發(fā)工具 Eval Board for XR16M654IJ-0B RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16M654IJ68 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
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