REV. 1.0.1 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.7 Programmable Baud Rate Generator with Fractional Di" />
參數(shù)資料
型號(hào): XR16M670IB25-F
廠商: Exar Corporation
文件頁數(shù): 3/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 32B 25BGA
標(biāo)準(zhǔn)包裝: 714
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 25-WFBGA
供應(yīng)商設(shè)備封裝: 25-BGA(3x3)
包裝: 托盤
XR16M670
11
REV. 1.0.1
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
2.7
Programmable Baud Rate Generator with Fractional Divisor
The M670 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.
The prescalers are controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler
to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/
16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling. For transmitter and receiver, the M670 provides
respective BRG divisors. The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL =
0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization
to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD
registers provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value
from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 3 shows the
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 3. At 8X sampling rate, these
data rates would double. And at 4X sampling rate, they would quadruple. Also, when using 8X sampling mode,
please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number.
When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the
following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
The closest divisor that is obtainable in the M670 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
2.7.1
Independent TX/RX BRG
The XR16M670 has two independent sets of TX and RX baud rate generator. Please see the Figure 7. TX and
RX can work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data
to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate
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