XR16M680
43
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
TABLE 16: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLM, DLL
(Both TX and RX)
DLM = 0x00 and DLL = 0x01. Only resets to these val-
ues during a power up. They do not reset when the
Reset Pin is asserted.
DLD
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 7-0 =0xX0 (Read-only)
Bits 7-4 = 0000 (Write-only)
SPR
Bits 7-0 = 0xFF
EMSR
Bits 7-0 = 0x00
FC
Bits 7-0 = 0x00
FCTR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
HIGH
RTS#
HIGH
DTR#
HIGH
INT
(16 Mode)
Three-State Condition
IRQ#
(68 Mode)
HIGH