參數(shù)資料
型號(hào): XR16M680IM48-0C-EB
廠商: Exar Corporation
文件頁數(shù): 55/57頁
文件大小: 0K
描述: EVAL BOARD FOR XR16M680-C 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16M680
7
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
1.0
PRODUCT DESCRIPTION
The XR16M680 (M680) is a high performance single channel UART. It has its set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, the M680 channel has 32 bytes of transmit and receive FIFOs, Automatic RTS/CTS Hardware
Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared encoder and decoder
(IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and
data rate up to 16 Mbps. The XR16M680 can operate from 1.62 to 3.63 volts. The M680 is fabricated with an
advanced CMOS process.
Larger FIFO
The M680 provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of 16 bytes
in the XR16L580. The M680 is designed to work with high performance data communication systems, that
requires fast data processing time. Increased performance is realized in the M680 by the larger transmit and
receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external
processor to handle more networking tasks within a given time. For example, the XR16L580 with a 16 byte
FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including
start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms
intervals. However with the 32 byte FIFO in the M680, the data buffer will not require unloading/loading for 6.1
ms. This increases the service interval giving the external CPU additional time for other applications and
reducing the overall UART interrupt servicing time. In addition, the selectable FIFO level trigger interrupt and
automatic hardware/software flow control is uniquely provided for maximum data throughput performance
especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s
bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The M680 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate. The device can
operate at 3.3V with a 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 32 MHz on
XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler
bit and sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the M680 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder,
modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning
off (Xon) software flow control with any incoming (RX) character. The M680 includes new features such as 9-
bit (Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate for TX and RX, fast IR mode
and fractional baud rate generator.
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