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參數(shù)資料
| 型號： | XR16M681IB25-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 64B 25BGA |
| 標(biāo)準(zhǔn)包裝： | 714 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS422，RS485 |
| 電源電壓： | 1.62 V ~ 3.63 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 25-WFBGA |
| 供應(yīng)商設(shè)備封裝： | 25-BGA（3x3） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1458 XR16M681IB25-F-ND |
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XR16M681
28
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
REV. 1.0.1
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xon or Xoff interrupt is cleared by a read to the ISR register. See EMSR[7].
Special character interrupt is cleared by a read to ISR register or after next character is received. See
EMSR[7].
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Wakeup interrupt is cleared by a read to ISR register.
]
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xon, Xoff or Special character)
7
1
0
CTS#, RTS# change of state
-
0
1
None (default) or Wakeup interrupt
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16M681IL24 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE |
| XR16M681IL24-0C-EB | 功能描述:界面開發(fā)工具 Eval Board for XR16M681IL24 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR16M681IL24-F | 功能描述:UART 接口集成電路 1.62-3.63V; 32-Byte FIFO & VLIO; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16M681IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE |
| XR16M681IL32-0C-EB | 功能描述:界面開發(fā)工具 Eval Board for XR16M681IL32 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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