REV. 1.0.1 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE For Power-Save, the UART internally isolates all of these input" />
參數(shù)資料
型號(hào): XR16M681IL32-0C-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 38/51頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16M681-C 32QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16M681
43
REV. 1.0.1
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
For Power-Save, the UART internally isolates all of these inputs (except the modem inputs and Reset pins) therefore elimi-
nating any unnecessary external buffers to keep the inputs steady. SEE”POWER-SAVE FEATURE” ON PAGE 21. To
achieve minimum power drain, the voltage at any of the inputs of the M681 should NOT be lower than its VCC supply.
AC ELECTRICAL CHARACTERISTICS
TA = -40O TO +85OC, VCC IS 1.62 TO 3.6V, 25 PF LOAD WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
1.8V ± 10%
MIN
MAX
LIMITS
2.5V ± 10%
MIN
MAX
LIMITS
3.3V ± 10%
MIN
MAX
UNIT
XTAL1
UART Crystal Frequency
24
MHz
ECLK
External Clock Frequency
40
64
80
MHz
TECLK
External Clock Time Period
12
7
6
ns
TAS
Address Setup Time
10
8
6
ns
TAH
Address Hold Time
3
2
ns
TCSL
Delay from CS# to LLA#/IOR#/IOW#
0
ns
TLLA
LLA# Strobe Width
10
ns
TRD
IOR# Strobe Width
40
25
20
ns
TLLAR
Delay from LLA# to IOR#
2
ns
TLLAW
Delay from LLA# to IOW#
2
ns
TDY
Read/Write Cycle Delay
40
25
20
ns
TRDV
Data Access Time
40
20
15
ns
TDD
Data Disable Time
20
10
ns
TWR
IOW# Strobe Width
10
ns
TDS
Data Setup Time
10
8
6
ns
TDH
Data Hold Time
3
2
ns
TWDO
Delay From IOW# To Output
50
ns
TMOD
Delay To Set Interrupt From MODEM
Input
50
ns
TRSI
Delay To Reset Interrupt From IOR#
50
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
45
ns
TSI
Delay From Start To Interrupt
45
ns
TINT
Delay From Initial INT Reset To
Transmit Start
8
24
8
24
8
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
45
ns
TSSR
Delay From Stop To Set RXRDY#
1
Bclk
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