REV. 1.0.2 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit i" />
參數(shù)資料
型號(hào): XR16M770IB25-F
廠商: Exar Corporation
文件頁數(shù): 25/52頁
文件大?。?/td> 0K
描述: IC UART FIFO 64B 25BGA
標(biāo)準(zhǔn)包裝: 714
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 25-WFBGA
供應(yīng)商設(shè)備封裝: 25-BGA(3x3)
包裝: 托盤
XR16M770
31
REV. 1.0.2
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 10: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity to mark, HIGH
1
Forced parity to space, LOW
BIT-2
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