FIGURE 10. RECEIVER O
參數(shù)資料
型號: XR16M770IL24-0B-EB
廠商: Exar Corporation
文件頁數(shù): 7/52頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16M770-B 24QFN
標準包裝: 1
系列: *
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
R egister (RSR)
R XFIFO 1
16X or 8X or 4X Clock
( DLD[5:4] )
Err
or
T
a
gs
(64
-se
ts
)
Er
ro
rT
ag
si
n
LS
R
b
its
4:
2
R eceive D ata Characters
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RH R Interrupt (ISR bit-2) program m ed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
R TS# de-asserts when data fills above the flow
control trigger level to suspend rem ote transm itter.
Enable by EFR bit-6=1, M C R bit-1.
R TS# re-asserts when data falls below the flow
control trigger level to restart rem ote transm itter.
Enable by EFR bit-6=1, M CR bit-1.
64 bytes by 11-bit wide
FIFO
Trigger=16
D ata falls to
8
D ata fills to
56
Exam ple
: - R X FIFO trigger level selected at 16 bytes
(See N ote Below )
XR16M770
15
REV. 1.0.2
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
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