REV. 1.0.3 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 2.14 Auto RTS Hysteresis The V2551 has a n" />
參數(shù)資料
型號: XR16V2551IM-F
廠商: Exar Corporation
文件頁數(shù): 9/49頁
文件大小: 0K
描述: IC UART FIFO 16B DUAL 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
XR16V2551
17
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
2.14
Auto RTS Hysteresis
The V2551 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one level above the selected RX trigger level in the trigger table
(Table 12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected RX
trigger level in the trigger table (Table 12). Under the above described conditions, the V2551 will continue to
accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is
asserted LOW (RTS On).
TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
1
4
0
4
8
1
8
14
4
14
8
2.15
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 10):
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
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