FIGURE 10. RECEIVER O
參數(shù)資料
型號: XR16V554IL-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 9/43頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16V554 48QFN
標準包裝: 1
系列: *
FIGURE 10. RECEIVER OPERATION IN FIFO
Receive Data Shift
R egister (RSR)
R XFIFO 1
16X C lock
E
rro
rT
ags
(16-sets
)
Er
ro
rT
ag
s
in
LS
R
bits
4:
2
R eceive D ata Characters
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RH R Interrupt (ISR bit-2) program m ed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Asking for stopping data when data fills above the flow
control trigger level to suspend rem ote transm itter.
Asking for sending data when data falls below the flow
control trigger level to restart rem ote transm itter.
16 bytes by 11-bit wide
FIFO
Trigger=8
D ata falls to
4
D ata fills to
14
Exam ple
: - R X FIFO trigger level selected at 8 bytes
(See N ote Below )
XR16V554/554D
17
REV. 1.0.3
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
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