參數(shù)資料
型號(hào): XR16V554IL-F
廠商: Exar Corporation
文件頁數(shù): 1/43頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B QUAD 48QFN
標(biāo)準(zhǔn)包裝: 260
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
規(guī)程: RS232
電源電壓: 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 托盤
其它名稱: 1016-1466
XR16V554IL-F-ND
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16V554/554D
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
JULY 2010
REV. 1.0.3
GENERAL DESCRIPTION
The XR16V554 (V554) is a quad Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
receive FIFO trigger levels and data rates of up to 4
Mbps at 3.3 V. Each UART has a set of registers that
provide the user with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The V554 is available in a 48-
pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin
LQFP packages. The 64-pin and 80-pin packages
only offer the 16 mode interface, but the 48- and 68-
pin packages offer an additional 68 mode interface
which
allows
easy
integration
with
Motorola
processors. The XR16V554IV (64-pin) offers three
state interrupt output while the XR16V554DIV
provides continuous interrupt output. The XR16V554
is compatible with the industry standard ST16C554.
FEATURES
Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C554A and Philip’s SC16C554B
Intel or Motorola Data Bus Interface select
Four independent UART channels
Register Set Compatible to 16C550
Data rates of up to 4 Mbps at 3.3 V and 3.125
Mbps at 2.5 V
16 byte Transmit FIFO
16 byte Receive FIFO with error tags
4 Selectable RX FIFO Trigger Levels
Full modem interface
2.25V to 3.6V supply operation
Crystal oscillator or external clock input
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FIGURE 1. XR16V554 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc / Buffer
Data Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG
TX & RX
UART
Regs
2.25V to 3.6 V VCC
GND
554BLK
TXB, RXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
16/68#
CSB#
INTA
INTB
IOW#
IOR#
Reset
INTSEL
TXRDY#A-D
RXRDY#A-D
UART Channel C
(same as Channel A)
TXA, RXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXC, RXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
UART Channel D
(same as Channel A)
TXD, RXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
CSC#
CSD#
INTC
INTD
* 5 Volt Tolerant Inputs
( Except XTAL1input)
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