REV. 1.0.4 INTSEL 38 - 65 6 I Interrupt Select (active high, input with internal pull" />
參數(shù)資料
型號(hào): XR16V564IL-F
廠(chǎng)商: Exar Corporation
文件頁(yè)數(shù): 51/54頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 32B QUAD 48QFN
標(biāo)準(zhǔn)包裝: 260
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 32 字節(jié)
規(guī)程: RS232
電源電壓: 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 托盤(pán)
XR16V564/564D
6
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.4
INTSEL
38
-
65
6
I
Interrupt Select (active high, input with internal pull-
down).
When 16/68# pin is HIGH for Intel bus interface, this
pin can be used in conjunction with MCR bit-3 to
enable or disable the INT A-D pins or override MCR
bit-3 and enable the interrupt outputs. Interrupt out-
puts are enabled continuously when this pin is HIGH.
MCR bit-3 enables and disables the interrupt output
pins. In this mode, MCR bit-3 is set to a logic 1 to
enable the continuous output. See MCR bit-3 descrip-
tion for full detail. This pin must be LOW in the Motor-
ola bus interface mode. For the 64 pin packages, this
pin is bonded to VCC internally in the XR16V564D so
the INT outputs operate in the continuous interrupt
mode. This pin is bonded to GND internally in the
XR16V564 and therefore requires setting MCR bit-3
for enabling the interrupt output pins.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
6
8
28
30
8
10
39
41
17
19
51
53
29
32
69
72
O
UART channels A-D Transmit Data and infrared trans-
mit data. Standard transmit and receive interface is
enabled when MCR[6] = 0. In this mode, the TX signal
will be a HIGH during reset, or idle (no data). Infrared
IrDA transmit and receive interface is enabled when
MCR[6] = 1. In the Infrared mode, the inactive state
(no data) for the Infrared encoder/decoder interface is
a logic 0.
RXA
RXB
RXC
RXD
48
13
22
36
62
20
29
51
7
29
41
63
17
44
57
4
I
UART channel A-D Receive Data or infrared receive
data. Normal receive data input must idle HIGH.
RTSA#
RTSB#
RTSC#
RTSD#
3
11
25
33
5
13
36
44
14
22
48
56
26
35
66
75
O
UART channels A-D Request-to-Send (active low) or
general purpose output. This output must be asserted
prior to using auto RTS flow control, see EFR[6],
MCR[1], and IER[6]. Also see
Figure 11. If these
outputs are not used, leave them unconnected.
CTSA#
CTSB#
CTSC#
CTSD#
1
12
23
35
2
16
33
47
11
25
45
59
23
38
63
78
I
UART channels A-D Clear-to-Send (active low) or gen-
eral purpose input. It can be used for auto CTS flow
control, see EFR[7], and IER[7]. Also see
These inputs should be connected to VCC when not
used.
DTRA#
DTRB#
DTRC#
DTRD#
-
3
15
34
46
12
24
46
58
24
37
64
77
O
UART channels A-D Data-Terminal-Ready (active low)
or general purpose output. If these outputs are not
used, leave them unconnected.
DSRA#
DSRB#
DSRC#
DSRD#
-
1
17
32
48
10
26
44
60
22
39
62
79
I
UART channels A-D Data-Set-Ready (active low) or
general purpose input. This input should be connected
to VCC when not used. This input has no effect on the
UART.
Pin Description
NAME
48-QFN
PIN #
64-LQFP
PIN #
68-PLCC
PIN #
80-LQFP
PIN #
TYPE
DESCRIPTION
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