REV. 1.0.4 2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO MCR[3]: INT Output Enable Enable or disable INT outputs to become active " />
參數(shù)資料
型號(hào)： XR16V564IV80-F
廠商： Exar Corporation
文件頁數(shù)： 27/54頁
文件大小： 0K
描述： IC UART FIFO 32B QUAD 80LQFP
標(biāo)準(zhǔn)包裝： 119
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 32 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（12x12）
包裝： 托盤
XR16V564/564D
33
REV. 1.0.4
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be LOW during 68 mode.
Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During internal loopback mode,
OP2# is HIGH.
Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW.
TABLE 14: INT OUTPUT MODES
PIN
BIT-3
INT A-D OUTPUTS IN 16 MODE
0
Three-State
0
1
Active
1
X
Active
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the V564 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4 = 1)
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be LOW during idle data conditions.
MCR[7]: Clock Prescaler Select (requires EFR bit-4 = 1)
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
INTSEL
MCR
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