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UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
XR17D152
REV. 1.2.0
II
5.2.3 TRANSMITTER OPERATION IN FIFO MODE........................................................................................................... 27
5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 27
F
IGURE
12. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
............................................................................................................ 27
5.3 RECEIVER ...................................................................................................................................................... 28
5.3.1 RECEIVE HOLDING REGISTER (RHR)..................................................................................................................... 28
F
IGURE
13. T
RANSMIITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
................................................................................... 28
5.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 29
5.3.3 RECEIVER OPERATION WITH FIFO......................................................................................................................... 29
F
IGURE
14. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
.................................................................................................................. 29
F
IGURE
15. R
ECEIVER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
......................................................................................... 29
5.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 30
T
ABLE
10: A
UTO
RTS/CTS
OR
DTR/DSR F
LOW
C
ONTROL
S
ELECTION
.......................................................................................... 30
F
IGURE
16. A
UTO
RTS/DTR
AND
CTS/DSR F
LOW
C
ONTROL
O
PERATION
...................................................................................... 31
5.5 INFRARED MODE .......................................................................................................................................... 32
F
IGURE
17. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
.......................................................................... 32
5.6 INTERNAL LOOPBACK ................................................................................................................................. 33
5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ...................................... 33
F
IGURE
18. I
NTERNAL
L
OOP
B
ACK
F
UNCTION
IN
EACH
UART C
HANNEL
.......................................................................................... 33
T
ABLE
11: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 34
T
ABLE
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4. ....... 35
5.8 REGISTERS .................................................................................................................................................... 36
5.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 36
5.8.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 36
5.8.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE................................................................ 36
5.8.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE.......................................................................................... 36
IER versus Receive FIFO Interrupt Mode Operation................................................................................................. 36
IER versus Receive/Transmit FIFO Polled Mode Operation..................................................................................... 36
5.8.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY............................................................................................ 37
T
ABLE
13: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
..................................................................................................................... 38
5.8.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY.................................................................................................. 39
T
ABLE
14: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
............................................................................................ 40
5.8.7 LINE CONTROL REGISTER (LCR) - READ/WRITE.................................................................................................. 41
5.8.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE ........................................................................................... 42
T
ABLE
15: P
ARITY
SELECTION
........................................................................................................................................................ 42
5.8.9 LINE STATUS REGISTER (LSR) - READ/ONLY....................................................................................................... 43
5.8.10 MODEM STATUS REGISTER (MSR) - READ-ONLY .............................................................................................. 44
5.8.11 MODEM STATUS REGISTER (MSR) - WRITE-ONLY............................................................................................. 45
T
ABLE
16: A
UTO
RS485 H
ALF
-
DUPLEX
D
IRECTION
C
ONTROL
D
ELAY
FROM
T
RANSMIT
-
TO
-R
ECEIVE
................................................. 45
5.8.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE................................................................................................. 46
5.8.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE.................................................................................... 46
5.8.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE..................................................................................... 47
T
ABLE
17: 16 S
ELECTABLE
H
YSTERESIS
L
EVELS
W
HEN
T
RIGGER
T
ABLE
-D
IS
S
ELECTED
................................................................ 47
T
ABLE
18: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
........................................................................................................................ 48
5.8.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ-ONLY ......................................................................... 49
5.8.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE-ONLY........................................................................ 49
5.8.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ-ONLY............................................................................ 49
5.8.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE-ONLY............................................................................ 49
T
ABLE
19: UART RESET CONDITIONS...................................................................................................................................... 50
6.0 PROGRAMMING EXAMPLES .............................................................................................................51
6.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS .................. 51
ABSOLUTE MAXIMUM RATINGS ..................................................................................52
ELECTRICAL CHARACTERISTICS................................................................................52
DC ELECTRICAL CHARACTERISTICS FOR 5V PCI B
US
I
NTERFACE
(VIO = 4.75-5.25V, VCC = 4.5-5.5V)
52
AC ELECTRICAL CHARACTERISTICS FOR 5V PCI B
US
I
NTERFACE
(VIO = 4.75-5.25V, VCC = 4.5-5.5V)
53
ELECTRICAL CHARACTERISTICS................................................................................54
DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI B
US
I
NTERFACE
(VIO = 3.0-3.6V, VCC = 3.0-5.5V)54
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI B
US
I
NTERFACE
(VIO = 3.0-3.6V, VCC = 3.0-5.5V)55
F
IGURE
19. T
IMING
F
OR
E
XTERNAL
C
LOCK
I
NPUT
AT
XTAL1 P
IN
.................................................................................................... 56
F
IGURE
20. PCI B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
R
EAD
AND
W
RITE
OPERATION
................................................................. 57
F
IGURE
21. D
EVICE
C
ONFIGURATION
AND
UART R
EGISTERS
R
EAD
O
PERATION
FOR
A
B
YTE
OR
DWORD ...................................... 58
F
IGURE
22. D
EVICE
C
ONFIGURATION
REGISTERS
, UART R
EGISTERS
AND
T
RANSMIT
D
ATA
B
URST
W
RITE
O
PERATION
..................... 59