REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 23 DVID [15:8] Device identification for the type of UART. The upper nibble i" />
參數(shù)資料
型號(hào)： XR17D158IV
廠商： Exar Corporation
文件頁數(shù)： 16/73頁
文件大?。?/td> 0K
描述： IC UART PCI BUS OCTAL 144LQFP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 60
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
xr
XR17D158
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
23
DVID [15:8]
Device identification for the type of UART. The upper nibble indicates it is a XR17Dxxx series with lower nibble
indicating the number of channels.
Examples:
XR17C158 or XR17D158 = 0x28
XR17C154 or XR17D154 = 0x24
XR17C152 or XR17D152 = 0x22
DREV [7:0]
Revision number of the XR17D158. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous write to all 8 UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data.
2.2.9
Multi-Purpose Inputs and Outputs
The D158 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to
be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to
generate an interrupt. The outputs can be set to be normal logic 1 or 0 state, or 3-state. Their functions and
definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all
8 pins are set for inputs, all 8 interrupts would be OR’ed together. The OR’ed interrupt is reported in the
channel 0 UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be
outputs and to the 3-state condition for signal sharing.
2.2.10
MPIO REGISTER
Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and outputs. Figure 8 shows the internal circuitry.
2.2.8
REGB Register
REGB[16](Read/Write)
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to all 8 UARTs configuration register.
REGB[19:17]
Reserved
REGB[20] (Write-Only)
Control the EECK, clock, output (pin 116) on the EEPROM interface.
REGB[21] (Write-Only)
Control the EECS, chips select, output (pin 115) to the EEPROM device.
REGB[22] (Write-Only)
EEDI (pin 114) data input. Write data to the EEPROM device.
REGB[23] (Read-Only)
EEDO (pin 113) data output. Read data from the EEPROM device.
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