參數(shù)資料
型號(hào)： XR19L210IL40-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 2/43頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L202 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR19L210
10
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
2.10.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.10.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
2.11
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the rising edge of RXD
(or falling edge of RX) of a start or a false start bit, an internal receiver counter starts counting at the 16X clock
rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled
and if it is still LOW it is validated as a start bit. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Each of the data, parity and stop bits is sampled at the middle of the bit to
prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading
the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately
updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
Transm it Data Shift Register
(TSR)
Transm it
Data Byte
Transm it
FIFO
16X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1,2 and Xon1,2 Reg.)
TXF IF O 1
THR Interrupt (ISR bit-1):
FIFO is Enabled by FCR bit-0=1
- W hen the TX FIFO falls below the
program m ed Trigger Level, and
- W hen the TX FIFO becom es em pty.
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