參數(shù)資料
型號: XR19L220IL40-0B-EB
廠商: Exar Corporation
文件頁數(shù): 40/43頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR19L202 40QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR19L220
6
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
2.0
FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L220 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L220 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
VCC
A0
A1
A2
UART_CS#
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART_INT
INT
Full RS-232
Interface
Intel Data Bus Interconnections
GND
UART_RESET
RESET
16/68#
RI
CD
DSR
CTS
RTS
DTR
RX
TX
PwrSave
Power-Save
VCC
A0
A1
A2
UART_CS#
R/W#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART_IRQ#
INT
Motorola Data Bus Interconnections
GND
UART_RESET#
RESET
RI
CD
DSR
CTS
RTS
DTR
RX
TX
PwrSave
VCC
16/68#
Full RS-232
Interface
Power-Save
4.7K
VCC
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