參數(shù)資料
型號: XR19L222IL64-0B-EB
廠商: Exar Corporation
文件頁數(shù): 52/53頁
文件大小: 0K
描述: EVAL BOARD FOR XR19L202 64QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR19L222
8
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
2.0
FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L222 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L222 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
VCC
DSRA
CTSA
RTSA
DTRA
RXDA
TXDA
RIA
CDA
RXB
DSRB
CTSB
RTSB
DTRB
RXDB
TXDB
RIB
CDB
GND
UART
Channel A
UART
Channel B
Full RS-232 Interface
Intel Data Bus Interconnections
TXB
Full RS-232 Interface
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
CSA#
CSB#
IOR#
IOW #
UART_INTB
UART_INTA
INTB
INTA
ACP
R_EN
RESET
R_EN
PWRSAVE
ACP
RXBSEL
FAST
UART_RESET
PW RSAVE
FAST
External IR or RS-422
Transceiver
VCC
RXB
DSRA
CTSA
RTSA
DTRA
RXDA
TXDA
RIA
CDA
TXB
DSRB
CTSB
RTSB
DTRB
RXDB
TXDB
RIB
CDB
GND
UART
Channel A
UART
Channel B
Full RS-232 Interface
Motorola Data Bus Interconnections
UART_IRQ#
INTA
VCC
INTB
(no connect)
R_EN
ACP
RXBSEL
FAST
PWRSAVE
RESET
UART_RESET
External IR or RS-422
transceiver
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
VCC
R/W#
IOW#
UART_CS#
CSA#
A3
CSB#
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