REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- " />
參數(shù)資料
型號: XR20M1170G16-0A-EB
廠商: Exar Corporation
文件頁數(shù): 18/56頁
文件大小: 0K
描述: EVAL BOARD FOR XR20M1170 16TSSOP
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR20M1170
次要屬性: I²C & SPI 接口
已供物品:
其它名稱: 1016-1614
XR20M1170G16-0A-EB-ND
XR20M1170
25
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
4.2
Transmit Holding Register (THR) - Write-Only
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
0x0B
IOState
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0C IOIntEna RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0D reserved
-
0
0x0E IOControl RD/WR
0
UART
SW
Reset
0
GPIO or
Modem
IO
IOLatch
0x0F
EFCR
RD/WR Fast IR
Mode
0
Auto
RS485
Invert
Auto
RS485
Enable
0
TX
Disable
RX
Disable
9-Bit
Mode
Baud Rate Generator Divisor
0x00
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR
≠0xBF
0x01
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x02
DLD
RD/WR
Bit-7
Bit-6
4X Mode 8X Mode
Frac-
tional
Divisor
Bit-3
Frac-
tional
Divisor
Bit-2
Frac-
tional
Divisor
Bit-1
Frac-
tional
Divisor
Bit-0
LCR[7]=1
LCR
≠0xBF
EFR[4]=1
Enhanced Registers
0x02
EFR
RD/WR
Auto
CTS
Enable
Auto RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
Soft-
ware
Flow
Cntl
Bit-3
Software
Flow Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
0x04
XON1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x05
XON2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x06
XOFF1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x07
XOFF2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
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