REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO address, it does not have to anything. If the address does not match its slave address, " />
參數(shù)資料
型號: XR20M1170IG16
廠商: Exar Corporation
文件頁數(shù): 11/56頁
文件大?。?/td> 0K
描述: IC UART FIFO I2C/SPI 64B 16TSSOP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 95
特點: *
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 2.25 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設(shè)備封裝: 16-TSSOP
包裝: 管件
XR20M1170
19
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
address, it does not have to anything. If the address does not match its slave address, then the receiver
should be disabled.
2.14.2
Auto Address Detection
Auto address detection mode is enabled when EFCR bit-0 = 1 and EFR bit-5 = 1. The desired slave address
will need to be written into the XOFF2 register. The receiver will try to detect an address byte that matches the
porgrammed character in the XOFF2 register. If the received byte is a data byte or an address byte that does
not match the programmed character in the XOFF2 register, the receiver will discard these data. Upon
receiving an address byte that matches the XOFF2 character, the receiver will be automatically enabled if not
already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the
parity error bit). The receiver also generates an LSR interrupt. The receiver will then receive the subsequent
data. If another address byte is received and this address does not match the programmed XOFF2 character,
then the receiver will automatically be disabled and the address byte is ignored. If the address byte matches
XOFF2, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit.
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