XR20M1170
24
I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.1.0
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
0x00
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0x00
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x01
IER
RD/WR
0/
Modem
Stat. Int.
Enable
RX Line
Stat. Int.
Enable
TX
Empty
Int
Enable
RX Data
Int.
Enable
CTS Int.
Enable
RTS Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0x02
ISR
RD
FIFOs
Enabled
FIFOs
Enabled
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
INT
Source
Bit-5
INT
Source
Bit-4
0x02
FCR
WR
RXFIFO
Trigger
RXFIFO
Trigger
0/
0
TX FIFO
Reset
RX FIFO
Reset
FIFOs
Enable
TXFIFO
Trigger
TXFIFO
Trigger
0x03
LCR
RD/WR Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Enable
Stop Bits
Word
Length
Bit-1
Word
Length
Bit-0
0x04
MCR
RD/WR
0/
Internal
Lopback
Enable
OP2#
(Internal)
OP1#
(Internal)/
RTS#
Output
Control
DTR#
Output
Control
LCR
≠0xBF
Clock
Pres-
caler
Select
IR Mode XonAny
Enable
TCR and
TLR
0x05
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX Par-
ity Error
RX
Overrun
Error
RX Data
Ready
0x06
MSR
RD
CD#
Input
RI# Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta RI#
Delta
DSR#
Delta
CTS#
See
0x07
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
See
0x06
TCR
RD/WR Resume
Bit-3
Resume
Bit-2
Resume
Bit-1
Resume
Bit-0
Halt
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt
Bit-0
See
0x07
TLR
RD/WR RX Trig
Bit-3
RX Trig
Bit-2
RX Trig
Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig
Bit-2
TX Trig
Bit-1
TX Trig
Bit-0
See
0x08
TXLVL
RD/WR
0
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x09
RXLVL
RD/WR
0
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0A
IODir
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0