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參數(shù)資料
| 型號： | XR20M1172L32-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 36/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR20M1172 32QFN |
| 標準包裝： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR20M1172 |
| 主要屬性： | 2 通道 |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
| 其它名稱： | 1016-1625 XR20M1172L32-0B-EB-ND |
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XR20M1172
41
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, TCR,
TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the programmed HALT level. RTS# will return LOW when FIFO data falls below the
programmed RESUME level. The RTS# output must be asserted (LOW) before the auto RTS can take effect.
RTS# pin will function as a general purpose output when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
4.21.1
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 8.
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| XR20M1280 | 制造商:EXAR 制造商全稱:EXAR 功能描述:I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS |
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| XR20M1280IL32-F | 功能描述:UART 接口集成電路 1Ch 12C/SPI UART w/ Lvl Shftrs & 8 GPIOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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