XR-2211
10
Rev. 3.01
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 10 the functions
of external components are defined as follows: R
0
and C
0
set the PLL center frequency, R
1
sets the system bandwidth,
and C
1
sets the loop filter time constant and the loop damping factor. C
F
and R
F
form a one-pole post-detection filter for
the FSK data output. The resistor R
B
from pin 7 to pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
Design Instructions:
The circuit of Figure 10can be tailored for any FSK decoding application by the choice of five key circuit components: R
0
,
R
1
, C
0
, C
1
and C
F
. For a given set of FSK mark and space frequencies, f
O
and f
1
, these parameters can be calculated as
follows:
(All resistance in ’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a)
Calculate PLL center frequency, f
O
:
f
O
F
1
·F
2
b)
Choose value of timing resistor R
0
, to be in the range of 10K to 100K . This choice is arbitrary. The recommended
value is R
0
= 20K . The final value of R
0
is normally fine-tuned with the series potentiometer, R
X
.
R
O
R
O
R
X
2
c)
Calculate value of C0 from design equation (1) or from Figure 7
C
O
1
R
0
· f
0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R
1
R
0
·f
0
(f
1
–f
2
)·2
e)
Calculate C1 to set loop damping. (See design equation 4):
Normally, = 0.5 is recommended.
C
1
1250·C
0
R
1
·
2