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參數(shù)資料
| 型號： | XR68C192CJTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFI DUAL 44PLCC |
| 標準包裝： | 500 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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XR68C92/192
21
Rev. 1.33
must be disabled and its interrupt must be masked. The
following table shows how to select the clock source for
the C/T when used in counter mode or timer mode:
ACR Bit-7: Baud rate table Select.
This bit is used to select between two sets of baud rate
tables. See Baudrate table on Page 18. It should be
changed only after both channels have been reset and
disabled.
0 = Set 1
1 = Set 2
ISR Bit-1: Receive ready A .
This bit is set when channel A's receive buffer (FIFO) is
filled above the programmed receive trigger level condi-
tion (see MR0A bit-6 and MR1A bit-6). For example, if
a RX trigger level of '6' is chosen, this bit will be set
whenever the RX FIFO contains six or more bytes. This
bit can be cleared by reading the data out of the FIFO
till it falls below the trigger level.
ISR Bit-2: Channel A change in break.
This bit is set when channel A receiver detects the
beginning or the end of a break condition. It is reset
when the CPU issues a channel A reset break change
interrupt command (CRA bits 7-4 = 0x5).
ISR Bit-3: Counter/Timer (C/T) ready.
In counter mode, this bit is set when the C/T reaches
terminal count. In timer mode, this bit is set each time
the C/T output switches from low to high (rising edge -
see Figure 2). In either mode, this bit is cleared by a
stop counter command.
ISR Bit-4: Transmit ready B.
This bit is set when channel B's transmit buffer (FIFO)
is filled below the programmed transmit trigger level
(see MR0B bits 5-4). For example, if a TX trigger level
of '4' is chosen, this bit will be set whenever the TX
FIFO has four or more empty locations. This bit can be
cleared by loading the TX FIFO above the trigger level.
ISR Bit-5: Receive ready B.
This bit is set when channel B's receive buffer (FIFO)
is filled above the programmed receive trigger level
condition (see MR0B bit-6 and MR1B bit-6). For ex-
ample, if a RX trigger level of '6' is chosen, this bit will
be set whenever the RX FIFO contains six or more
bytes. This bit can be cleared by reading the data out
of the FIFO till it falls below the trigger level.
ISR Bit-6. Channel B change in break.
This bit is set when channel B receiver detects the
beginning or the end of a break condition. It is reset
when the CPU issues a channel B reset break change
interrupt command (CRB bits 7-4 = 0x5).
ISR Bit-7. Input port change status.
This bit is set when a change of state has occurred at
the IP0, IP1, IP2, or IP3 inputs, and that event has been
enabled to cause an interrupt by programming ACR
Bits 3-0. This bit is cleared when the CPU reads the
input port change register.
INTERRUPT STATUS REGISTER (ISR)
This register provides the status of all potential interrupt
sources. The contents of this register are logically
“AND”-ed with the contents of the interrupt mask
register, and the results are “OR”-ed. The resulting
signal is inverted to produce the -INT output. All active
interrupt sources are visible by reading the ISR, re-
gardless of the contents of the interrupt mask register.
Reading the ISR has no effect on any interrupt source.
Each active interrupt source must be cleared in a
source-specific fashion to clear the ISR. All interrupt
sources are cleared when the XR68C92/192 is reset.4
ISR Bit-0: Transmit ready A.
This bit is set when channel A's transmit buffer (FIFO)
is filled below the programmed transmit trigger level
(see MR0A bits 5-4). For example, if a TX trigger level
of '4' is chosen, this bit will be set whenever the TX
FIFO has four or more empty locations. This bit can be
cleared by loading the TX FIFO above the trigger level.
ACR
C/T
Clock Source
Bits 6:4
Mode
0 0 0
Counter
External (IP2)
0 0 1
Counter
TXAClk1-Transmit A 1X clock
0 1 0
Counter
TXBClk1-Transmit B 1X clock
0 1 1
Counter
Crystal or External Clock
(XTAL1/Clk) Divided by 16
1 0 0
Timer
External (IP2)
1 0 1
Timer
External (IP2) Divided by 16
1 1 0
Timer
Crystal or External Clock
(XTAL1/Clk)
1 1 1
Timer
Crystal or External Clock
(XTAL1/Clk) Divided by 16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR68C192CP | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| XR68C192CV | 制造商:Exar Corporation 功能描述: |
| XR68C192CV-0A-EVB | 功能描述:界面開發(fā)工具 Supports 68C192 44ld TQFP, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR68C192CV-F | 功能描述:UART 接口集成電路 Dual Channel UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR68C192CVTR-F | 功能描述:UART 接口集成電路 Dual Channel UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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